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ENSEMBLE® 3000 Series LDS3506 Low Density Server OpenVPX Xeon-D

Product Description

Rugged OpenVPX™ Ensemble® LDS3506 processing module that seamlessly integrates Intel’s Xeon® D-series processor (formerly codenamed “Broadwell DE”) with Xilinx’s powerful Ultrascale™ FPGA in a SWaP-constrained 3U package. This dense union of best available commercial-item general processing and FPGA resources produces a highly versatile, affordable and interoperable building block for embedded, high-performance compute applications with additional low-latency, refresh and mission capabilities.

The Ensemble LDS3506 leverages Mercury’s fourth generation of highly SWaP-efficient packaging technology to securely deliver the Xeon® D-series processors for reliable deployment in scalable subsystems right to the tactical edge. The Ensemble LDS3506 secures and cools the best commercial technology to produce the densest and most powerful combination of general server-class and low-latency front-end FPGA processing in an open systems architecture module that is designed and made in the USA.

The LDS3506 provides x4 Gen3 PCIe connectivity across the data plane via Xilinx’s FPGA device, with multiple DMA-enabled Non-Transparent Bridge (NTB) interfaces, giving users the versatility needed to construct powerful processing subsystems quickly.  The module’s latest Xilinx FPGA hosts Mercury’s Protocol Offload Engine Technology (POET) to give each module the ability to refresh its mission capability, provide information assurance abilities, or even refresh or upgrade its switch fabric itself without affecting any hardware.

The Ensemble LDS3506 supports open data movement middleware, including Open MPI and OpenMPI/OFEDTM, VITA 46.11 system management, and standard optimized math libraries.  

  • Features
  • Benefits
  • Specs
  • Request Form
• 3U OpenVPX™ compliant VITA 65/46/48 (VPX-REDI) module
• 8-core Broadwell DE Intel® Xeon® D family server-class processor
• Xilinx® UltraScaleTM FPGA with dual x4 PCIe data plane and Ethernet control plane
• 512 GFLOPS peak processing power in a single slot
• Dual 10 Gigabit Ethernet interfaces for sensor I/O or inter-processor communication
• x8 PCIe expansion plane for additional I/O or offload
• Mercury MultiCore Plus® software infrastructure support 
The Ensemble LDS3506 is a dense, 3U processing OpenVPX building block for high-compute, SWaP-constrained applications with a large front-end, low-latency FPGA capability that is ideally suited to EW, SIGINT and EO/IR sensor chain applications. The union of the latest general processing devices from Intel and most capable FPGA resources from Xilinx creates a new paradigm in high-compute, low-density embedded processing.

Main processor: 

  • Intel 8-core, 64 bit, Xeon D-1548
  • 512 GFLOPS peak performance
  • AVX 2.0


  • Xilinx UltraScale XCKU040 or XCKU060

System Memory: 

  • 8 or 16GB DDR4-2133 (32 GB planned)


  • 3U OpenVPX, single width (1-inch)
  • Module packages:
    • Air-cooled (lab)
    • Conduction-cooled
    • Air Flow-By


  • OpenVPX VITA 65/46/48 (VPX – REDI)