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ENSEMBLE® 6000 Series LDS6520 Low Density Server OpenVPX i7

Product Description

The Ensemble® 6000 Series OpenVPX™ (VITA 65) Intel® Core i7 Dual-Core LDS6520 Module integrates a high-end Nehalem-class dual-core Intel Core i7 processor, a next-generation FPGA for both fabric bridging and user-application functions, and high-bandwidth on-board and off-board communication fabrics in a single 6U OpenVPX slot. By leveraging Intel high-density Core i7 processing with on-board integrated highperformance PCI Express infrastructure and I/O mezzanine sites, the LDS6520 delivers a well-balanced and scalable computing architecture that can provide processing and I/O functionality for highendradar, signals intelligence, and image processing applications.
  • Features
  • Benefits
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  • Intel 64-bit Core i7 610E Arrandale dual-core processor running at up to 2.53 GHz with 46 peak GFLOPS
  • First embedded computing product to combine processing power of Ineld Core i7 family with high-speed serial RapidIO fabric interface
  • On-board Altera Stratix IV FPGA provides streaming bridge for high-bandwidth, low-latency data80-
  • 80-lane Gen2 PCI Express switch for onboard switching and off-board expansion
  • Advanced system management functionality architected in Open VPX secification enables remote system monitoring, alarm management, and hardware revision and health status
  • Rugged low-density server with high-end processing and fabric I/O capabilities
  • 6U OpenVPX™-compliant VITA 65/46/48 (VPX-REDI) module
  • High-performance Intel® Core i7 Arrandale (Nehalem-class) dual-core processor at up to 2.53 GHz with 46 GFLOPS peak performance
  • Serial RapidIO® and/or 10 Gigabit Ethernet fabric enabledIntegrated 80-lane PCIe switching infrastructure for on-board and off-board co-processing expansion-plane communications
  • Mercury MultiCore Plus® software infrastructure support

Intel Arrandale Nehalem-Class 32-nm Processor
Dual-core: 2.0 GHz to 2.53 GHz
Peak performance: 46 GFLOPS (estimate)
Threads per core: 2
Intel Virtualization Technology
DDR3-1066: 4 GB with ECC (up to 8 GB future capability)
Raw memory bandwidth: 21.3 GB/s (total)
BIOS SPI flash: 8 MB
NAND flash: 4 GB

Altera Stratix® IV EP4SGX180 FPGA
Logic elements: 175,000
Internal memory: 11.7 Mb
18x18 multipliers: 920
SerDes: 16
Each SerDes: 600 Mbp to 6.25 Gbps
184 GMACs: 200 MHz
1066-MT/s DDR3 SDRAM: Up to 128 MB
Provides fabric bridging to data plane
Can act as co-processor to execute iFFT/FFT, image
   or signal processing
Configured from CPU or dedicated configuration ROM

IPMI (System Management)
On-board IPMI Controller
Voltage and temperature monitor
Geographical address monitor
Power/reset control
FRU and on-board EEPROM interfaces
FPGA, CPU, and CPLD interfaces

Ethernet Connections1000BASE-BX Ethernet to P4 connector: 2
    OpenVPX Control Plane
10/100/1000BASE-T Ethernet to P4 connector: 1
    Accessible via OpenVPX RTM or external chassis interface
10/100/1000BASE-T Ethernet connection: 1
    To front panel (air-cooled module)
    or backplane (conduction-cooled module)
Ethernet functions supported by the chipset include:
    UDP, TCP, SCTP, ARP, IPv4, IPv6, IEEE1588,
    flow control, 802.1P (priority), and 802.1Q (VLAN)

OpenVPX Multi-Plane ArchitectureSystem Management via IPMB-A and IPMB-B link on
    P0 management plane
Dual 4x Serial RapidIO or 10 Gigabit Ethernet interfaces on
    P1 data plane
Full x16 or dual x8 PCIe expansion plane
Dual 1000BASE-BX Ethernet control plane

PMC-X/XMC Sites
Mezzanine sites: 1 PMC/XMC, 1 XMC only
PCI-X-to-PCIe bridge
    Connects PMC site to on-board PCI Express switch
PMC PCI support: 33 and 66 MHz
PMC PCI-X support: 66, 100, and 133 MHz
PMC user-defined I/O from P4 to backplane
PCIe XMC sites per VITA 42.3 with XMC user-defined
    I/O from J6 to backplane

Additional I/O Capabilities
RS-232 serial interface to front panel: 1
    (air-cooled) or backplane (conduction-cooled)
    Configurable for RS-422 signaling when routed to backplane
Front-panel USB 2.0 interface: 1
    (air-cooled configurations only)
USB 2.0 interfaces to backplane: 2
SATA interfaces to backplane: 2
Single-ended GPIO interfaces to backplane: 8
System signals to backplane
    NVMRO, ChassisTest, Environmental Bypass, MemoryClear

Mechanical
6U VPX (air-cooled and conduction-cooled)
1.0” slot pitch
OpenVPX and VPX REDI

Environmental  

Air-Cooled – Mercury Rugged Level 1
Temperature
    Operating:* -25°C to +55°C
    Storage; -55°C to +85°C
       *Customer must maintain required cfm level.
Humidity
    Operating: 5-95%, non-condensing
Vibration: 0.04 g2/Hz; 20 to 2000 Hz, 1 hr/axis
Shock: 50g, z-axis; 80g, x-, y-axes; 11 ms half-sine
Altitude
    Operating:* 0-30,000 ft
    *Customer must maintain required cfm level.

Conduction-Cooled – Mercury Rugged Level 3Temperature
    Operating: -40°C to +71°C at the card edge*
    Storage: -55°C to +125°C
         *Customer chassis must maintain card edge at 71°C.
Humidity
  Operating: 0-100%
Vibration: 0.1 g2/Hz, based on 5-2000 Hz, 1 hr/axis
Shock: 50g, z-axis; 80g, x-, y-axes; 11 ms half-sine
Altitude
   Operating: 0-70,000 ft

Compliance
OpenVPX System Specifi cation encompasses
    VITA 46.0, 46.3, 46.4, 46.6, 46.11
Compatible with VITA 65
VITA 46/48.1/48.2 (REDI)
Serial RapidIO, PCI Express, 10 Gigabit Ethernet