FPGA IP

Block Downconverters

Block downconverters take real samples of a contiguous block of frequencies centered about a desired intermediate frequency (IF) and convert them to samples of a baseband, complex signal. Fs/4 block downconverters translate the input signal spectrum, located at ¾ (or optionally ¼) of the input sample rate, Fs, to baseband. Fs/4 block downconverters can have the largest possible bandwidth of 75% or more of Fs/2.

Highlights:

  • Take in real A/D samples in band centered at intermediate frequency (IF) and convert to baseband
  • “Fs/4” block downconverters assume IF centered at ¾*Fs (or optionally ¼*Fs) and convert to baseband
    • Final sample rate is Fs/2
    • BW is 75-80% of Fs/2
Block_Downconverters

 

Block Downconverters DSP IP Offerings


epgFs4Dec2Path1 – Block Downconverter

It converts an IF centered at ¾*Fs to baseband. The complex output is in 1 paths (1 complex output samples per clock). With an inherent decimation of 2, then, an Fs of 2*Fclk is supported. For a clock rate of 250 MHz, this means a real, input sample rate of 500 MS/s in 2 input paths. A version is available that allows the IF center frequency to be specified as either ¾*Fs, for even Nyquist Zone signals, or ¼*Fs, for odd Nyquist Zone IFs.

Highlights:

  • Converts an IF centered at ¾*Fs or ¼*Fs to baseband*
  • Decimation by 2 and complex output in 1 path
    • => Fs = 2*Fclk
     

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epgFs4Dec2Path2 – Block downconverter 

It converts an IF centered at ¾*Fs to baseband. The complex output is in 2 paths (2 complex output samples per clock). With an inherent decimation of 2, then, an Fs of 4*Fclk is supported. For a clock rate of 250 MHz, this means a real, input sample rate of 1 GS/s in 4 input paths. A version is available that allows the IF center frequency to be specified as either ¾*Fs, for even Nyquist Zone signals, or ¼*Fs, for odd Nyquist Zone IFs.

Highlights:

  • Similar to epgFs4Dec2Path1 but output in 2 paths
    • => Fs = 4*Fclk
     

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epgFs4Dec2Path4 – Block downconverter 

It works the same way as epgFs4Dec2Path2. The complex output, however, is in 4 paths (4 complex output samples per clock). With an inherent decimation of 2, then, an Fs of 8*Fclk is supported. For a clock rate of 250 MHz, this means a real, input sample rate of 2 GS/s in 8 input paths. Aversion is available that allows the IF center frequency to be specified as either ¾*Fs, for even Nyquist Zone signals, or ¼*Fs, for odd Nyquist Zone IFs.

Highlights:

  • Similar to epgFs4Dec2Path2 but output in 4 paths
    • => Fs = 8*Fclk
     

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epgFs4Dec2Path8 – Block downconverter

It works the same way as epgFs4Dec2Path2. The complex output, however, is in 4 paths (4 complex output samples per clock). With an inherent decimation of 2, then, an Fs of 8*Fclk is supported. For a clock rate of 250 MHz, this means a real, input sample rate of 2 GS/s in 8 input paths.

Highlights:

  • Similar to epgFs4Dec2Path2 but output in 8 paths
    • => Fs = 16*Fclk
     

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