FPGA IP

Block Upconverters

Interpolators and b lock upconverters take complex samples of a wideband signal centered at baseband and convert them to a desired IF. Complex form will be maintained if the D/A has built in interpolation/processing, or the real part may be output if the D/A has no such processing. Fs/4 block upconverters place the signal spectrum at ¾ (or possibly ¼) of the final output sample rate. They can have the largest possible bandwidth of 75% or more of the two-sided signal bandwidth (the input sample rate).

Highlights:

  • Takes in complex (usually) baseband samples and converts to real (can be complex) intermediate frequency (IF) samples
  • “Fs/4” block upconverters assume IF centered at ¾*Fs (or optionally ¼*Fs)
    • Final sample rate, FDAC, is 2*Fs
    • BW is 75-80% of Fs
       

Block_Upconverters 


Block Upconverters DSP IP Offerings


epgFs4Xmtr4Ci8Ro – Block Upconverters

A block upconverter that converts a complex signal centered at baseband to ¾*FDAC and outputs the real part. The complex input is in 4 paths (4 complex input samples per clock). With an inherent interpolation of 2, then, an FDAC of 8*Fclk is supported. A clock rate of 250 MHz results in a real output sample rate of 2.0 GS/s in 8 output paths.

Highlights:

  • Converts a complex signal centered at baseband to ¾*FDAC and outputs the real part.
  • Interpolation by 2 and complex input in 4 paths
    • Fs = 4*Fclk
    • FDAC = 8*Fclk
     

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epgFs4Xmtr2Ci8Ro – Block Upconverters

A block upconverter similar to epgFs4Xmtr4Ci8Ro. This IP has the ability to place the output signal spectrum in either the first (odd) or second (even) Nyquist Zones. Note that even with the same DAC clock, this upconverter supports only ½ the signal bandwidth of epgFs4Xmtr4Ci8Ro. The advantage is that the input data rate is reduced proportionally (½).

Highlights:

  • Converts a complex signal centered at baseband to ¾*FDAC and outputs the real part.
  • Interpolation by 4 and complex input in 2 paths
    • Fs = 2*Fclk
    • FDAC = 8*Fclk
    • Output can be placed in either 2nd (even – default) of 1st (odd) Nyquist Zone for operation with RZ or RF/mix mode DACs
     

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epgFs4Xmtr1Ci8Ro – Block Upconverters

A block upconverter that works the same way as epgFs4Xmtr4Ci8Ro. The complex input, however, is in 1 path (1 complex input sample per clock). With a total interpolation of 8, then, an FDAC of 8*Fclk is supported. For a clock rate of 250 MHz, this means a real output sample rate of 2.0 GS/s in 8 output paths. In addition, this IP has the ability to place the output signal spectrum in either the first (odd) or second (even) Nyquist Zones. Note that even with the same DAC clock, this upconverter supports only ¼ the signal bandwidth of epgFs4Xmtr4Ci8Ro. The advantage is that the input data rate is reduced proportionally (¼).

Highlights:

  • Converts a complex signal centered at baseband to ¾*FDAC and outputs the real part.
  • Interpolation by 8 and complex input in 1 path
    • Fs = Fclk
    • FDAC = 8*Fclk
    • Output can be placed in either 2nd (even – default) of 1st (odd) Nyquist Zone for operation with RZ or RF/mix mode DACs
     

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