Receive IP Cores

These are FPGA cores that receive raw, real samples from an A/D at sample rate Fs, and process them to desired center frequencies, signal bandwidths/sample rates and frequency responses. They then pass that information downstream for further exploitation. They include block downconverters, tunable downconverters, channelizer and Hilbert transformer.


  • Accepts raw, real samples from A/D
  • Process from/ to desired center frequency, signal bandwidth, frequency response, sample rate and convert to complex
  • Pass downstream, generally at much-reduced sample rate

Examples of Receive IP include:

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