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PCIe-to-Serial RapidIO Intelligent Bridge IP Core

Product Description

The PCIe-to-Serial RapidIO Intelligent Bridge IP Core is architected for applications requiring high-bandwidth bridging between PCI Express® (PCIe) devices and serial RapidIO® digital signal processors (DSPs), processors, and switch fabric. The IP connects a serial RapidIO port operating up to 5.0 GHz to an 8x or 4x PCI Express Gen1 or 4x Gen2 through an intelligent non-transparent bridge. Sophisticated queuing within the intelligent bridge assures the highest utilization of available port bandwidth.

The PCIe-to-Serial RapidIO Intelligent Bridge IP Core is designed for bridging the growing number of RapidIO and PCI Express applications. The core is independent of physical layer designs, implementation tools, and target technology, and is capable of addressing a variety of solutions for ASICs and FPGAs.

  • Features
  • Benefits
  • Specs
  • Request Form
  • Industry-standard, high-performance, packet-switching technologies
  • Independent of physical layer designs, implementation tools, and target technology
  • Sophisticated queuing
  • Multiple DMA engines
  • Serial RapidIO mailboxes and interrupts
  • Address mapping
  • Support for both ASICs and FPGAs
  • Industry-standard, high-performance, packet-based interconnect technology
  • Provides both serial RapidIO and PCI Express endpoints
  • Implements an advanced buffering scheme, address remapping, and MSI/MSI-x interrupts
  • Includes a Multi-Channel DMA controller
  • Targets both FPGA and ASIC technologies

Language: System Verilog HDL
Synthesis: Synopsys/Synplicity/Altera
Technology: 0.09 µm or better ASICs and Xilinx or Altera FPGAs
Simulation: Model Technology
Support for:
    RapidIO 1.2
    1.25, 2.5, 3.125, 5.0 GHz serial speeds
    1x, 4x lanes
    Error management extensions
    34-bit addressing
    All legal data payload sizes up to 256 bytes
    Input/output and message-passing protocols
    Receiver-controlled and transmitter-based flow control
    All transaction flows and priorities
    Multicast event support
 PCI Express 1.1
    2.5 GHz serial speeds
    1x, 2x, 4x, 8x lanes
PCI Express 2.0
    5.0 GHz serial speeds
    1x, 2x, 4x lanes

Availability and Serviceability  Available now

Product Options
Integrated circuit
Single or multi-use license
Soft IP core: RTL source code, synthesis scripts, and so on
Comprehensive documentation package
Support for Altera® and Xilinx® FPGAs
OVM-based testbench support

Compliance
  RapidIO specification, Revision 1.3, 2.1 5 GHz
  PCI Express specification, Revision 1.1 and 2.0