×

Register now for complete access to all Resource Hub content!

First Name
Last Name
Company
Job Title
Country
State
Opt me in to receive communications from Mercury Systems
Thank you!
Error - something went wrong!
   

Enabling edge processing with stacked, high-speed DDR4 and DDR5 memory

In military environments, seconds can be the difference between mission success or failure and life or death. System malfunction or failure due to poor signal integrity within integrated circuits and embedded board designs leads to catastrophic events. 

The problems are stacking up

The complexity of die stacking and wire bonding increases with each additional die needed to design high-density memory, such as a single 16GB DDR4 device or a custom multi-chip module (MCM) device. With so many circuits in a tightly stacked configuration, signal integrity is at the forefront of design considerations. 

Previous Asset
Understanding Broadband Electrical Behavior of Through-Silicon-Via (TSV)
Understanding Broadband Electrical Behavior of Through-Silicon-Via (TSV)

At the epicenter of modern 3D and 2.5D package design is through-silicon-via (TSV) technology. TSVs facili...

Next Asset
Military-Grade Microelectronics Packaging for the 21st Century
Military-Grade Microelectronics Packaging for the 21st Century

We discuss our proposal for a new microelectronics packaging platform addressing the practical needs of the...