WEDPN8M64V-XB2X

Docs & Specs

Data Sheet

Application Note

Overview

Model:  WEDPN8M64V-XB2X
64MB 8Mx64 Synchronous DRAM (SDRAM)

The 64MByte (512Mb) SDRAM is a high-speed CMOS, dynamic random-access memory using 4 chips containing 134,217,728 bits. Each chip is internally configured as a quad-bank DRAM with a synchronous interface. Each of the chip's 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.

Features

  • Registered for enhanced performance of bus speeds:  100, 125, 133MHz
  • Package:  219 Plastic Ball Grid Array (PBGA), 21 x 21mm
  • Single 3.3V ±0.3V power supply
  • Fully Synchronous; all signals registered on positive edge of system clock cycle
  • Internal pipelined operation; column address can be changed every clock cycle
  • Internal banks for hiding row access/precharge
  • Programmable Burst length 1,2,4,8 or full page
  • Commercial, Industrial and Military Temperature Ranges
  • Organized as 8M x 64 User Configurable as 2x8Mx32 or 4x8Mx16
  • Weight:  WEDPN8M64V-XB2X - 2 grams typical

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