Docs & Specs

Data Sheet

Application Notes


Model:  WEDPY256K72V-XBX
256Kx72 Synchronous Pipeline SRAM

The WEDPY256K72V-XBX employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. The 16Mb Synchronous SRAMs integrate two 256K x 36 SRAMs into a single PBGA package to provide 256K x 72 configuration. All synchronous inputs are controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, and active LOW chip selects (CS#). Asynchronous inputs include the output enable (OE1#/OE2#), clock (CLK).


  • Fast clock speed:  100, 133, 150, 166 and 200** MHz
  • Fast access time:  5.0, 4.0, 3.8, 3.5, 3.1ns
  • +3.3V power supply (VCC)
  • +2.5V output buffer supply (VCCQ)
  • Single-cycle deselect
  • Common data inputs and data outputs
  • Clock-controlled and registered addresses, data I/Os and control signals
  • SNOOZE MODE for reduced-power standby
  • Individual BYTE WRITE control and GLOBAL WRITE
  • Six chip enables for simple depth expansion and address pipeline
  • Internally self-timed WRITE cycle
  • Burst control (interleaved or linear burst)


  • 159-bump PBGA package, 14mm x 22mm
  • Commercial, industrial, and military temperature ranges
  • User configurable as 512K x 36, or 1M x 18

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