The WEDPY256K72V-XBX employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. The 16Mb Synchronous SRAMs integrate two 256K x 36 SRAMs into a single PBGA package to provide 256K x 72 configuration. All synchronous inputs are controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, and active LOW chip selects (CS#). Asynchronous inputs include the output enable (OE1#/OE2#), clock (CLK).
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