WEDPZ512K72V-XBX

Docs & Specs

Data Sheet

Application Notes

Overview

Model:  WEDPZ512K72V-XBX
512K x 72 Synchronous Pipeline Burst ZBL SRAM

The Mercury Systems' SyncBurst - SRAM employs high-speed, low-power CMOS design that is fabricated using an advanced CMOS process. Mercury Systems' 32Mb SyncBurst SRAMs integrate two 512K x 36 SSRAMs into a single BGA package to provide 512K x 72 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The ZBL or Zero Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied œHigh or Low. Asynchronous inputs include the sleep mode enable (ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals.

Features:

  • Fast clock speed:  150, 133, and 100MHz
  • Fast access times:  3.8ns, 4.2ns, and 5.0ns
  • Fast OE# access times:  3.8ns, 4.2ns, and 5.0ns
  • High performance 3-1-1-1 access rate
  • 3.3V ± 5% power supply
  • I/O supply voltage 3.3V or 2.5V
  • Common data inputs and data outputs
  • Byte write enable and global write control
  • Six chip enables for depth expansion and address pipeline
  • Internally self-timed write cycle
  • Burst control pin (interleaved or linear burst sequence)
  • Automatic power-down for portable applications
  • Commercial, industrial and military temperature ranges

Packaging:

  • 152 PBGA package 17 x 23mm

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