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Training Course Information

PowerPC® (PPC) Module

The PowerPC® Processor optimization course shows users how to optimize the PPC architecture in the Mercury environment. Floating-point processing with the Mercury Scientific Algorithm Library (SAL) and the Mercury PixL image processing algorithm library using the PPC is emphasized throughout the course. Optimization techniques and dangers are covered in detail.

The PowerPC® course is designed to work in conjunction with the MCP course, and it is recommended that the two courses be taken sequentially to ensure users obtain the knowledge and expertise necessary for performance improvement in typical DSP applications.

The PowerPC® and MCP courses enable users to reduce application development time by approximately 30 days or more.


DAY 1 

  • Introduction to Mercury Embedded Processor Ecosystems 
  • Review of Backplanes and Form Factors
  • Review of the High Compute Density (HCD) cards , SBCs IO and Carrier Boards
  • Review of the Switch Card
  • Processor Architectural Considerations
  • Floating-Point Array Considerations
  • Speed-Complexity Considerations
  • Compiler Considerations
  • Using the Data Cache Efficiently 
  • Data Cache and Instruction Cache Sizes
  • Data Cache Architecture Considerations
  • Strip-Mining
  • Timing Implications
  • Speed-Complexity Considerations
  • Integer and Floating Point-Specific PowerPC and AltiVec Considerations 
  • The Rename Registers
  • Arithmetic Normalization Considerations
  • Parallelization Implications

Laboratory Exercises 

DAY 2 

  • The Level 2 Cache 
  • Performance Implications
  • Access Speed
  • Coding Implications
  • Speed-Complexity Tradeoffs
  • Virtual Address Translation 
  • The Role of the PTE
  • Performance Implications of the Translation LookAside Buffer (TLB)
  • Optimization with the Block Address Translation (BAT) Registers
  • Designing your Algorithm for Optimal TLB Usage
  • Mercury SAL and C type Vector calls 
  • How and when to use prefetch
  • Alignment and its affect on performance
  • Compiler flags
  • Strip-mining down to the register level
  • Review of the more common open SAL calls
  • Optimal use of SAL calls for algorithm efficiency and fast data access
  • Using IO Interfaces ( optional ) 
  • MCP DMA and Device Control Commands
  • Sample Program
  • Optimization Considerations
  • Other I/O Devices

Review and Discussion of Student Applications 
Laboratory Exercises 

Course length:

2 days