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Optimal Performance and Integration of FPGAs in the Mercury Multicomputer Fabrics

This course shows users how to optimize their applications on the FPGA architecture in the Mercury environment. Fixed-point processing with the Mercury FPGA Compute Node (FCN) Developer Kit (FDK) and the optimal use of FPGA design tools is emphasized throughout the course. Optimization techniques and potential pitfalls are covered.

The FPGA course is designed to work in conjunction with the MCOE course, and the AltiVec PPC course as well, and it is recommended that the three courses be taken sequentially to ensure users obtain the knowledge and expertise necessary for performance improvement in typical DSP applications.

The FPGA, PowerPC and MCOE courses enable users to reduce application development time by weeks or even months. Large performance improvements are demonstrated which can save you significant time, hardware and money.

Prerequisites:

We assume that everyone has a basic knowledge of digital design fundamentals, VHDL, Xilinx ISE, ModelSim, Synthesis tools, Xilinx P&R, Virtex-II topology, and MCOE.

Knowledge of Matlab, Simulink and the Xilinx tools: Core Generator and System Generator or Synplify DSP are also quite useful and highly recommended.

Suggested courses (or the equivalent thereof):
See Xilinx web site Intro to VHDL
Advanced VHDL
Fundamentals of FPGA Design
Design for performance
Advanced FPGA Implementation
DSP Design Flow (System Generator)
DSP Implementation Techniques (Theoretical)
See the Mathworks website
Simulink
Simulinx for DSP Design
See Mentor Graphics website
Modelsim modeling and simulation tool
Leonardo / Precision systhesis tool
See Synplicity web site
Synplify Pro synthesis tool
See Denali web site for Optional Memory tools.

Note: Synplify Pro, Mentor Graphics Leonardo/ precision and Xilinx XST are all synthesis tools. Currently Mercury uses Synplify Pro and is experimenting with the other tools.

Course length:

2 days

Syllabus:

DAY 1

  • Provide an understanding of the scalable rapid development platform and methodology
  • Become familiar with FPGA Hardware that is ready to deploy
  • Experiment with the software and VHDL cores to accelerate development
  • Integrate with high level design tools to accelerate development even more
  • Provide a good understanding of the Hardware layout of the Mercury FPGA boards
  • Review the capabilities of Xilinx chips used on Mercury FPGA / FCN boards
  • Examine footprint of Mercury RaceWay DRAM SRAM and IO cores
  • Run Diagnostics
  • Power on Self Test (POST) and CheckMc
  • Boot up and launching an application on the FPGAs
  • The Default Mercury Bit stream MDB)
  • Memory checkers
  • Become familiar with operations from the conventional processors on the fabric or bus
  • Controlling the FPGA
  • Data transfer and synchronization
  • Provide insight on working Inside the FPGA
  • Provide a top-level understanding of FDK 2

Get a detailed understanding of key FDK interfaces and their value:
  • RoC
  • ICR
  • FcnMemory
  • IO interfaces
  • See how FCN applications are composed from VHDL IP cores
  • Become familiar with the PAL/APP abstraction
  • Learn how to use the "fcn_ring_defs"
  • See the whole picture of FDK specific design methodology
  • Gain an understanding of logical design and physical design
  • Experiment with functional simulation, verification IP and Bus Functional Models (BFMs)
  • Run labs through place and route
  • Run examples to gain an understanding of the run-time environment

DAY 2

  • Provide understanding of FDK / MCOE Interaction
  • Learn how to transfer data and synchronization with DMS (Endpoint IP)
  • Become familiar with using DX data transfer functions with FDK
  • Learn about the FABROM
  • Perform more lab activities
  • Build a simple FCN application from "scratch"
  • Experience RoC debugging made easy
  • Experiment with XILINX core generator
  • FFTs
  • optimization
  • Experiment with using XILINX System Generator or Synplify DSP tools
  • Simulink
  • Filter design
  • Building custom blocks
  • Black box wrappers for Mercury VHDL

More labs Time Permitting
  • Solutions to anticipated pitfalls
  • More Model Based Design
  • MGT / SFPDP (Gigabit SERDES)
  • LVDS / IO (Parallel I/O)
  • Other IO options

Optional Reading:
Sections of the 'IP Developer's Guide' that you should read in advance include:

  • The Development Process
  • RoC Bus Interface
  • ICR Bus Interface
  • DMS Interface
  • FcnMemory Generic Interface