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Simulation and Verification Environment (SVE)

Product Description

Simulation and Verification Environment (SVE) for end-to-end FPGA application modeling and verification

  • Compliance with industry-standard System Verilog-based OVM environment
  • Concurrent operation of various number and types of interfaces with synchronization between them
  • Programmable data/traffic generation and response checking
  • Error insertion/detection
  • Code and functional coverage as a measure of completeness
  • Configurable symbol or bit serial interface
  • Library of pre-built directed, constrained random, and performance test cases for testing of specific functionality and detecting corner cases
  • Directed, constrained-random performance tests using a unified API
  • Sparse memory for Bus Functional Models
  • Deposit of data files in memories at time 0
  • Serial interfaces that can run in parallel mode to improve simulation time


SVE for end-to-end FPGA application modeling and verification

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